1. Field of the Invention
The present invention relates generally to a semiconductor device such as a large scale integrated circuit device (LSI) and, more particularly, a semiconductor integrated circuit device having a field effect transistor driven by a low power supply voltage which can be interconnected to an analog IC (Integrated Circuit) (a linear IC) driven by a high power supply voltage. The present invention is particularly useful for a semiconductor device of a so-called CMOS (Complementary-Metal Oxide Semiconductor) type. The present invention also relates to a manufacturing method of such semiconductor devices.
2. Description of The Background Art
When the present invention is applied to an MOS type LSI which can be connected to an analog IC chip, the most preferable result can be obtained. The MOS type LSI has a logic circuit therein. FIG. 20 is a block diagram schematically showing an MOS type LSI connected to an analog IC. FIG. 21 is a plan view showing a planar arrangement of the MOS type LSI shown in FIG. 20. FIG. 22 is a sectional view taken along a line XXII--XXII in FIG. 21. A structure of a conventional MOS type LSI will be described hereinafter with reference to these figures.
Referring to FIG. 20, an MOS type LSI 100 is connected to an analog IC 200 with a pull up resistor R connected to a power supply voltage (12V) being interposed. MOS type LSI 100 has a pad 55 as a connecting terminal to analog IC 200. Pad 55 is connected to the drain of an n channel-open-drain-transistor 50. The n channel-open-drain-transistor is a transistor having a drain with an output terminal pad connected thereto. The gate of n channel-open-drain-transistor 50 receives a signal ("High" or "Low") from an internal logic circuit 80 through a CMOS inverter. The CMOS inverter is comprised of an n channel MOS transistor 60 and a p channel MOS transistor 70.
Referring to FIG. 21, n channel-open-drain-transistor 50 has a gate electrode 56, a source region 57 and a drain region 58. N channel MOS transistor 60 has a gate electrode 61, a source region 62 and a drain region 63. A p channel MOS transistor 70 has a gate electrode 71, a source region 72 and a drain region 73. Each transistor has a source region, a drain region and a gate electrode connected to an interconnection through contact holes ch.
Referring to FIG. 22, each of transistors 50, 60, 70 is formed in a p type silicon substrate 1. In p type silicon substrate 1, a p type well 2 and an n type well 3 are formed. n channel-open-drain-transistor 50 and n channel MOS transistor 60 are formed in p type well 2. p channel MOS transistor 70 is formed in n type well 3. p.sup.+ inversion preventing region 4 and a thick isolation oxide film 5 thereon are formed in order to electrically isolate transistors 50, 60, 70 from each other. A gate electrode of each of transistors is formed of a polycrystalline silicon layer 7 and a molybdenum silicon layer 8. Polycrystalline silicon layer 7 is formed on the surface of p type well 2 or n type well 3 with a gate oxide film 6 interposed. Source/drain regions of n channel-open-drain-transistor 50 and n channel MOS transistor 60 are comprised of an n.sup.- source/drain region 9 and an n.sup.+ source/drain region 10. A source/drain region of p channel MOS transistor 70 is comprised of a p.sup.+ source/drain region 22. An interlayer insulating layer 11 is formed to cover each of transistors 50, 60, 70. An interconnection layer 12 is provided to be in contact with each of the source/drain regions through each of the contact hole formed in interlayer insulating film 11.
An MOS type LSI structured as mentioned above will be described. Referring to FIG. 20, when a signal output from internal logic circuit 80 through a CMOS inverter is "High", a high voltage is applied to the gate of n channel-open-drain-transistor 50. At this time, n channel-open-drain-transistor 50 is turned on. Current flows from pad 55 to the drain of n channel-open-drain-transistor 50. At this time, a power supply voltage (12V) is distributed correspondingly to values of pull up resistor R and a resistor r of n channel-open-drain-transistor and transmitted to analog IC.
Conversely, when the signal output from internal logic circuit 80 through the CMOS inverter is "low", a low voltage is applied to the gate of n channel-open-drain-transistor 50, so that n channel-open-drain-transistor 50 is turned off. Current does not flow from pad 55 to the drain of n channel-open-drain-transistor 50. As a result, power supply voltage (12V) is transmitted to analog IC 200.
As described above, a drain breakdown voltage of n channel-open-drain-transistor 50 should be over 12V.
FIG. 25 includes a partial plan view (A) showing an enlargement of n channel-open-drain-transistor 50 or n channel MOS transistor 60, and a partial sectional view (B) showing a section taken along line B--B of the partial plan view (A). With reference to FIG. 25(A), drain region 58 (63) has an n.sup.+ impurity diffusion region 58a (63a) with its boundary region extended slightly outward as indicated by a dotted line. Therefore, n.sup.+ impurity diffusion region 58a (63a) overlaps with p.sup.+ inversion preventing region 4 as shown in FIG. 25(B). As a result, a drain breakdown voltage is reduced and determined by the overlapped portion.
In a conventional MOS type LSI, as shown in FIG. 22, n channel MOS transistor 60 connected to internal logic circuit 80 and n channel-open-drain-transistor 50 connected to pad 55 have the same structure. That is, n channel-open-drain-transistor 50 is structured to be driven by a power supply voltage of 5V, as n channel MOS transistor 60. This results in a problem that only a small margin in breakdown voltage specification is allowed for n channel-open-drain-transistor 50. For example, a surge breakdown voltage which is measured by capacitor charging method (one type of a surge breakdown testing method) on condition of 200 pF and 0.OMEGA. cannot reach .+-.300V or more.
FIG. 24 is a enlarged partial sectional view showing one portion of n channel MOS transistor 50 or 60. Polycrystalline silicon layer 7 and molybdenum silicide layer 8 are formed on gate oxide film 6. An oxide film 20 is formed on sidewalls of polycrystalline silicon layer 7 and molybdenum silicide layer 8 forming a gate electrode. Under a sidewall oxide film 20, n.sup.- source/drain region 9 is formed. N.sup.+ source/drain region 10 is formed to connect with n.sup.- source/drain region 9. In the structure shown in FIG. 24, sidewall oxide film 20 is formed of a film having fine step coverage such as a TEOS film (a silicon oxide film formed by a CVD method using Tetra-Ethyl-Ortho-Silicate as raw material). The TEOS film, however, has the property of holding a high density of trapped carriers therein, so that a problem exists that the aforementioned surge breakdown voltage of the n channel-open-drain-transistor decreases more.
Furthermore, the gate electrode has a two-layer structure comprised of polycrystalline silicon layer 7 and a molybdenum silicide layer 8. Because of a difference of etching speeds for the polycrystalline silicon layer and the molybdenum silicide layer, a side portion of polycrystalline silicon layer 7a forming a lower layer is frequently etched to a greater degree than molybdenum silicide layer 8 of an upper layer as shown in FIG. 23. Polycrystalline silicon layer 7a is, so-called, side-etched. Then, the surge breakdown voltage decreases even more.
N channel-open-drain-transistor 50 has a drain connected to pad 55. Pad 55 is connected to external analog IC 200 which is different from MOS type LSI 100. An external surge is directly applied through pad 55 to the drain of n channel-open-drain-transistor 50. Therefore, a surge breakdown voltage of n channel-open-drain-transistor 50 should be higher than a breakdown voltage of n channel MOS transistor 60 constituting the CMOS inverter or the n channel MOS transistor constituting internal logic circuit 80. However, each of the n channel MOS transistors constituting MOS type LSI 100 is formed on the same p type silicon substrate 1, that is, the same p type well 2. As a result, all n channel MOS transistors including n channel-open-drain-transistor 50 have the same breakdown voltage specification.
As a degree of integration of a semiconductor integrated circuit device becomes higher, transistors constituting internal logic circuit 80 are more and more miniaturized. Channel lengths of the miniaturized MOS transistors are becoming shorter. In order to obtain a predetermined drain breakdown voltage in an MOS transistor having such a short channel length, the MOS transistor has an LDD structure. For example, as shown in FIG. 22, n channel MOS transistor 50 or 60 has an LDD structure formed of n.sup.- source/drain region 9 and n.sup.+ source/drain region 10 as a source or a drain region. Also, as a measure to prevent a harmful effect by hot electrons generated in a field effect transistor having a short channel length, an impurity concentration of n.sup.- source/drain region 9 is restricted to a low value. Under the circumstances, a problem exists that it is difficult for a drain breakdown voltage and a surge breakdown voltage of an n channel-open-drain-transistor connected to an external IC to satisfy a prescribed specification.